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Learn about the tiniest new transistors that will power this decade
The most advanced chips built on next-gen manufacturing processes will rely on 'gate-all-around' transistors with 'nanosheets'. Let's unpack the engineering.
A heated week in chip land! 🔥 Samsung is launching their 3 nanometer process this week (seemingly beating TSMC to the punch by a few months), while TSMC keeps banging the drum about progress in their 2 nanometer process. The chips built on these most advanced manufacturing processes will rely on gate-all-around transistors with nanosheets. This new kid on the block will replace the older so-called FinFET transistors, which are running out of steam and cannot keep Moore's Law going. So what the heck is a 'nanosheet'? What's gate-all-around? Why is it better? What's all the fuss about!? ⁉️Let me take you along for a ride through some key chip designs. I hope it helps you make sense of the headlines that you'll find in my weekly newsletter. 🤓 Disclaimer: I will by no means be complete in my story and I will definitely be cutting corners, but I'm trying to make this as accessible as possible.
So let's start with a visualization. Imagine a chip as a metropolis. It's a busy place, with lots of buildings, skyscrapers, highways. And everywhere you look on the street, you see doors. 🚪 Billions of them. Thankfully, each door can be reached by the metropolis' intricate road network. If you want to get anything done in this town, you'll have to start opening doors to find what you're looking for.
Now let's dip our toes in the real tech. So, a chip contains billions of transistors with gates(doors). All these transistors are interconnected (roads) and they act as switches for electrical current (that's you, opening doors). Gates turns the transistors on and off, either allowing or preventing current to pass through. This allows the electrical currents to access, send, receive and process digital data as instructions and information. 0️⃣1️⃣1️⃣0️⃣1️⃣0️⃣1️⃣0️⃣
To be an efficient switch, a transistor needs to do three things extremely well: allow as much current to flow when it's on ⚡️ (drive current), allow as little current to flow when it's off 🛑(prevent leakage) and to switch between on and off as quickly as possible 🔄 (performance).
Enter the transistor designs.
💡 The classical transistor is called the planar transistor, because it brings together the key elements of the transistor on a two-dimensional plane: the gate(which modulates conductivity through a channel), the source(where drive current enters the channel) and the drain (where the current leaves the channel) are built on a base of the semiconducting material silicon. This transistor concept was industrialized in the 1950/60s and was highly suited for mass production and miniaturization by means of optical lithography. Transistor counts per chip quickly shot up, giving rise to Moore's Law and the chip industry as a whole. 📈
For many years, the performance of the planar transistor could be increased by shrinking the gate length. But as the gate shrank, the transistor's electrical performance started to suffer. The smaller the planar transistor, the more it leaked current. 👎 In the 2000s, at around the 20 nanometer node, this challenge drove the industry to look at alternative transistor designs.
💡 Engineers worked out that you could exert more control over the flow of current in the channel by raising it above the plane of the silicon, like a fin in the water. The industry made the leap from 2D planar transistors to 3D FinFET (fin field-effect transistor) transistors. In FinFET transistors, the gate wraps around the channel on three sides of a silicon fin, instead of only across its top like in planar transistors. This creates an inversion layer with a much larger surface area. That larger area gives the gate far more control over the flow of current through the transistor, while more current can flow through, there's less leakage, and a lower gate voltage is needed to operate the transistor. All good news! In addition, the vertical geometry of the FinFET allowed engineers to pack more transistors on a chip, driving Moore's Law further. The result was a chip with better performance, lower power consumption and a clear roadmap through the 2010s. 🙌😎
But Moore's Law is relentless. It was only a matter of time before FinFET technology would run out of steam. At the chip nodes that TSMC and Samsung are now rolling out, they are starting to hit the limits of how high fins can go and how many fins they can place side-by-side to boost current-carrying capacity without suffering from (you guessed it) electrical challenges.
💡 To further improve control of the transistor channel, engineers worked out that they could replace the vertical fin with a stack of horizontal sheets. This concept gave rise to the "gate-all-around" field-effect transistors: GAA transistors for short, or GAAFET if you want to be precise. According to their public statements, Samsung will start using these transistors in their new 3nm node (marketing dubbed it “MBCFET”), while TSMC is sticking with FinFETs for its 3nm but will go for GAA at 2nm.
Gate-all-around transistors use stacked nanosheets. These separate horizontal sheets are vertically stacked so that the gate surrounds the channel on all four sides, further reducing leakage and increasing drive current. That means superior electrical signals pass through and between the transistors, boosting performance of the chip. Additionally, chipmakers gain flexibility to vary the width of the nanosheets in order to best suit a particular chip design. Wide nanosheets mean higher and better drive current, while narrow nanosheets can optimize power consumption. 👍
As the chip industry marches from the nanometer era into the Angstrom era, there's nothing stopping the engineers and scientists from dreaming up the future. In fact, this industry's relentless focus on innovation has generated an R&D pipeline that's filled with transistor concepts for the next 20 years. 🔥
It's an exciting time to be part of this industry.